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| MD7101_A01 Preliminary 2.4GHz FSK Receiver www..com Rx module specification MD7101_A01 PRELIMINARY (Oct, 2003, Version 1.0) AMIC Technology, Corp. www..com MD7101_A01 General Description The receiver module is designed for 2.4GHz ISM band wireless applications using AMIC A7101 FSK transceiver. This module features a fully programmable frequency synthesizer, which is base on 100KHz reference frequency and 300uA charge pump output current. The data rate is 57.6Kbps or 64Kbps. Electrical specification Item Supply voltage Current consumption Frequency Rx sensitivity Modulation Channel spacing Channel number Interface Dimension Operating temperature Specification 3 - 5V 6uA(typical) @sleep mode (regulator off) 10mA(typical) @sleep mode (regulator on) 12mA(typical) @stand-by mode 40mA(typical) @Rx mode 2416 - 2478 MHz -80 dBm (max) FSK 2 MHz 32 6 & 3 pin 1.27mm header 35(L) x 19(W) x 10(H) mm3 0 - 50 Remark BER1E-3 PRELIMINARY (Oct, 2003, Version 0.0) 1 AMIC Technology, Corp. www..com MD7101_A01 Interface Pin Number J1-3 J1-4 J1-5 J1-6 J1-7 J1-8 J2-1 J2-2 J2-3 Pin Name VIN EN_REG SPI_LATCH SPI_CLOCK SPI_DATA GND MUTE EN_AFC RXDATA Description Supply voltage. Voltage regulator enable input, active high (VIN). Latch for SPI interface. Clock for SPI interface. Data for SPI interface. Ground. Receiver mute control output, active low (open drain). AFC circuit control input, active high. Receiver data output. Note Option. Option. Option. PRELIMINARY (Oct, 2003, Version 0.0) 2 AMIC Technology, Corp. www..com MD7101_A01 Serial to Parallel Interface (SPI) The SPI bus consists of three signals: SPI_DATA, SPI_CLOCK, and SPI_LATCH. This interface is used for external base-band controller to communicate with internal registers. The contents of the registers are shown in the following register description sections. After setting SPI_LATCH signal to "Low" state, data on SPI_DATA is shifted into the internal shift register on the rising edge of SPI_CLOCK with MSB going in first. SPI_LATCH should be asserted at the end to latch the data packet into the register according to the address bits, bit 0 through bit 3, for each of the registers. All registers can only be written into except the Status Register which can only be read. When the content of the Status Register need to be fetched by external controller, external baseband controller need to make sure that the address bits are pointing to address location 0x0 for proper read operation. After the address bits are shifted into the SPI interface and latched by asserting SPI_LATCH, the SPI interface will be in Read Mode and the content of the Status Register will be shifted out on SPI_DATA pin. When all 12 status bits have been shifted out, the SPI bus will be put back to Write Mode automatically. A. Register Description Note: Convention used: 1: Logic level "ONE". 0: Logic level "ZERO". X: Don't care. Synthesizer Configuration Register I (Write only / Address 0xf) Bit 15 Bit 14 Bit 13 MB6 MB5 MB4 Bit12 MB3 Bit11 MB2 Bit10 MB1 Bit9 MB0 Bit8 MA4 Bit7 MA3 Bit6 MA2 Bit5 MA1 Bit4 MA0 Bit3 1 Bit2 1 Bit 1 1 Bit 0 1 Synthesizer Configuration Register II (Write only / Address 0x7) Bit 15 Bit 14 Bit 13 X MB9 MB8 Bit12 MB7 Bit11 R7 Bit10 R6 Bit9 R5 Bit8 R4 Bit7 R3 Bit6 R2 Bit5 R1 Bit4 R0 Bit3 0 Bit2 1 Bit 1 1 Bit 0 1 Synthesizer Configuration Register I and Synthesizer Configuration Register II control synthesizer frequency settings where MA[4:0]: A counter[4:0] . Valid range is from 0 to 31. MB[9:0]: B counter[9:0] . Valid range is from 0 to 1023. R[7:0]: R counter[7:0] . Valid range is from 2 to 255, for this module must be set to 0x78 for proper operation. The content of A, B and R registers are in unsigned binary format (i.e., 111112 = 3110). The equation for setting the synthesizer frequency is: fvco = fcrystal * (32*B + A) / R, (B A). For example : If fvco = 2450MHz , fcrysta = 12MHz , freference = 100KHz. Then R = fcrysta / freference = 120 =011110002 , B = 765 = 10111111012 , A = 20 = 101002. PRELIMINARY (Oct, 2003, Version 0.0) 3 AMIC Technology, Corp. www..com MD7101_A01 Crystal Control Register (Write only / Address 0xb) Bit 15 Bit 14 Bit 13 Bit12 Bit11 Bit10 0 DP TXH2 TXH1 TXH0 TXL2 Bit9 TXL1 Bit8 TXL0 Bit7 FX3 Bit6 FX2 Bit5 FX1 Bit4 FX0 Bit3 1 Bit2 0 Bit 1 1 Bit 0 1 DP: Data Polarity. This control bit sets data output polarity. 0: Data is inverted. 1: Normal. TXH[2:0]: Must be set to 0x0 for proper operation. TXL[2:0]: Must be set to 0x0 for proper operation. FX[3:0]: Must be set to 0x0 for proper operation. VCO Control Register (Write only / Address 0x3) Bit 15 Bit 14 Bit 13 VTH2 VTH1 VTH0 Bit12 T1 Bit11 T0 Bit10 HP0 Bit9 CP2 Bit8 CP1 Bit7 CP0 Bit6 VC2 Bit5 VC1 Bit4 VC0 Bit3 0 Bit2 0 Bit 1 1 Bit 0 1 VTH[2:0]: Set VCO tuning voltage range, for this module must be set to 0x6 for proper operation. 0x0 = 0.3 to VDD-0.3V 0x2 = 0.5 to VDD-0.5V 0x4 = 0.7 to VDD-0.7V 0x6 = 0.9 to VDD-0.9V , , , , 0x1 = 0.4 to VDD-0.4V 0x3 = 0.6 to VDD-0.6V 0x5 = 0.8 to VDD-0.8V 0x7 = 1.0 to VDD-1.0V , , , , T[1:0]: Reserved. Must be set to 0x0 for proper operation. HP0: RF output power level control. 0: Low power output (-16 dBm). 1: High power output (-6 dBm). CP[2]: Reserved. Must be set to 0x0 for proper operation. CP[1:0]: Charge pump output current control, for this module must be set to 0x1(300uA) for proper operation. 0x0 = 100uA 0x2 = 500uA , 0x1 = 300uA , , 0x3 = 700uA , VC[2:0]: Reserved. Must be set to 0x4 for proper operation. RX Control Register (Write only / Address 0xd) Bit 15 Bit 14 Bit 13 T2 T1 T0 Bit12 MT2 Bit11 MT1 Bit10 MT0 Bit9 MTC Bit8 DM4 Bit7 DM3 Bit6 DM2 Bit5 DMI Bit4 DM0 Bit3 1 Bit2 1 Bit 1 0 Bit 0 1 T[2:0]: Reserved. Must be set to 0x0 for proper operation. MT[2:0]: Internal voltage threshold level for mute output (pin 37). 0x0 = 0.581*VDD 0x2 = 0.452*VDD 0x4 = 0.323*VDD 0x6 = 0.194*VDD , , , , 0x1 = 0.516*VDD 0x3 = 0.387*VDD 0x5 = 0.258*VDD 0x7 = 0.129*VDD , , , , MTC: RXDATA mute function enable. 0: Disable mute function. 1: Enable mute function. When RSSI output voltage level is higher than the threshold set by MT[2:0], RXDATA becomes inactive and pull high. PRELIMINARY (Oct, 2003, Version 0.0) 4 AMIC Technology, Corp. www..com MD7101_A01 DM[4:0]: Reference voltage level for demodulator tank center frequency tuning. Valid range is from 0x1f to 0x6. The setting of DM varies with the voltage reference level such that when DM = 0x6 voltage reference = 0.9V and when DM = 0x1f voltage reference = 2.4V. For this module must be set to 0x0 for proper operation. Mode Select Register (Write only / Address 0x5) Bit 15 Bit 14 Bit 13 X X X Bit12 X Bit11 X Bit10 SC1 Bit9 SC0 Bit8 XOE Bit7 CM Bit6 EXTB Bit5 MD1 Bit4 MD0 Bit3 0 Bit2 1 Bit 1 0 Bit 0 1 SC[1:0]: Status Register bit 6 control. Depends on the setting of SC[1:0], bit 6 of the Status Register can represent system error flag, Battery-low detect or PLL lock detect. [1:0] = 10: System Error. [1:0] = 11: Battery-low detect. [1:0] = 0X: PLL lock detect. XOE: Crystal oscillator buffer output enable. 0: Output enable. 1: Output disable. The output will be forced to low level at this setting. CM: Reserved. Must be set to 1 for proper operation. EXTB: Operating mode selection. 0: external mode. Operation mode is determined by external pin MODSEL0 and MODSEL1. 1: internal mode. Operation mode is determined by setting of MD[1:0]. MD[1:0]: Internal mode selection. [1:0] = 00: Sleep mode. Transceiver circuit is turned off. [1:0] = 01: Stand-by mode. X'TAL oscillator is turned on. [1:0] = 10: Transmit mode. [1:0] = 11: Receive mode. Status Register (Read only / Address 0x0) SR15 SR14 SR13 SR12 SR11 SR10 X X X X X X SR9 X SR8 X SR7 X SR6 S/B/P SR5 X SR4 X SR3 0 SR2 0 SR1 0 SR0 0 S/B/P: Depends on the setting of SC[1:0] in Mode Select Register, this bit can be used to reflect the status of System Error, Battery-low detect . System Error: 0: Normal; 1: Error. Battery-low detect: 0: Battery supply voltage below threshold. 1: Normal. PLL lock detect: 0: Unlock. 1: Lock. SR[3:0]: Address bits. PRELIMINARY (Oct, 2003, Version 0.0) 5 AMIC Technology, Corp. www..com MD7101_A01 B. SPI Timing Diagram Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 VH VI SPI_DATA SPI_CLOCK tCS tCH tCWH tCWL tEW tES SPI_LATCH Figure 3. SPI WRITE mode timing diagram After reading 12 bits, SPI is set to write mode SR0 SR1 SR2 SR3 SR4 SR5 SR6 SR7 SR11 SR12 SR13 SR14 SR15 Bit15 Bit14 SPI_DATA SPI_CLOCK SPI_LATCH Figure 4. SPI READ mode timing diagram PRELIMINARY (Oct, 2003, Version 0.0) 6 AMIC Technology, Corp. www..com MD7101_A01 C. SPI Timing Specification Parameter The High level of voltage The low level of voltage SPI_DATA to SPI_CLOCK setup time SPI_CLOCK to SPI_DATA hold time SPI_CLOCK pulse width high SPI_CLOCK pulse width low SPI_CLOCK to SPI_LATCH setup time SPI_LATCH pulse width Conditions Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Table 5. 50 10 50 50 50 50 Value Min VCC-0.4 0.4 Typ Max V V ns ns ns ns ns ns Units Symbol VH Vl tCE tCH tCWH tCWL tES tEW PRELIMINARY (Oct, 2003, Version 0.0) 7 AMIC Technology, Corp. www..com MD7101_A01 Module setup procedure: Step 1: Supply DC voltage to VIN. Step 2: Reset IC by setting SPI_CLOCK and SPI _LATCH to logic high simultaneously for more than 1 us. Step 3: Setup IC's internal control registers by configuring the followings: Synthesizer Configuration Register I, Synthesizer Configuration Register II, VCO Control Register, RX Control Register, and the Mode Select Register. All registers should be written to in the order specified above. a. Synthesizer Configuration Register I and II: Set VCO center frequency. b. VCO Control Register: Set VCO tuning range and charge pump output current. c. RX Control Register: Set mute threshold level, RXDATA mute function and reference voltage for demodulator tank center frequency tuning. When AFC function is used, DM[4:0] must be set to 0x0 for proper operation. Step 4: Set IC to Stand-by mode. For internal mode operation, set Mode Select Register to 0x05D5, then wait about 10mS. Step 5: Set IC to RX mode. For internal mode operation, set Mode Select Register to 0x05F5. Whenever frequency is to be changed, or system error has been detected (by reading from the Status Register) the IC must be reset by repeating step 2, 3-a, 4 and 5. PRELIMINARY (Oct, 2003, Version 0.0) 8 AMIC Technology, Corp. www..com MD7101_A01 PC board layout and dimension drawing Figure 1: Dimension Drawing Figure 2: Top Layer Layout PRELIMINARY (Oct, 2003, Version 0.0) 9 AMIC Technology, Corp. www..com MD7101_A01 Figure 3: Bottom Layer Layout Figure 4: Top Layer Placement PRELIMINARY (Oct, 2003, Version 0.0) 10 AMIC Technology, Corp. www..com MD7101_A01 Figure 5: Bottom layer Placement PRELIMINARY (Oct, 2003, Version 0.0) 11 AMIC Technology, Corp. |
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